Micron Launches Xccela™ Consortium to Promote High-Speed, Low Signal Count Octal Interface Bus and Ecosystem

December 15, 2016

Enabling a new generation of instant-on applications in the connected world

BOISE, Idaho, Dec. 15, 2016 (GLOBE NEWSWIRE) — Micron Technology, Inc. (NASDAQ:MU) today announced the creation of the Xccela™ Consortium for semiconductor and electronics companies. The mission of the consortium is to promote the Xccela Bus interface as an open standard for a new type of digital interconnect and data communications bus suitable for volatile and nonvolatile memories as well as other types of integrated circuits. To better highlight the accelerated performance that applications can achieve by using the bus and supported devices, Micron has rebranded its previously announced XTRMFlash™ and XTRMBus™ to Xccela™ Flash and Xccela™ Bus.

Micron, Winbond Electronics, GigaDevice Semiconductor, and AP Memory Technology are the initial members of the consortium and will work with other member companies to accelerate the industry efforts to bring a broad set of Xccela Bus compliant memories, controllers, ASICs, SoCs, and other devices to the market.

Since the advent of the smart phone, people have become accustomed to graphical user interfaces, instant-on responsiveness, portability, constant connectivity, and much more from their modern day electronic devices. This expectation is becoming the norm as we cram more and more smart electronics into our cars, our living space, and our lives. Meeting the needs of the demanding digital user calls for high performance system buses to accommodate firmware and software execution as well as data processing and storage. Current system bus interfaces often require the tradeoff between performance and footprint, either the high performance of a high pin-count parallel interface or the small active signal footprint of a serial interface. Xccela Bus changes that.

The Xccela Bus is the next generation of system buses that combines accelerated performance with a small signal count, the best of both worlds. In its first iteration, the Xccela Bus and its interface can facilitate data transfers up to 400MB/s (3.2Gbps) utilizing just 11 active bus signals, enabling extremely fast data transfers while paving the way for simpler system designs. “The Xccela Bus enables Micron’s Xccela Flash memory to be a disruptive solution that offers the highest level of direct code execution performance in a NOR Flash while having dramatically lower pin counts than that of traditional code execution parallel NOR Flash. The performance and benefits of Xccela Flash has garnered much excitement across automotive, industrial multimarket, consumer, and networking segments,” stated Richard De Caro, director of NOR Flash for

Micron’s Embedded Business Unit. “In order to proliferate this game changing new interface and level of performance, and to benefit the semiconductor industry as a whole, Micron is making the Xccela Bus interface an open standard.”

“Winbond is excited to be part of the Xccela Consortium. We are eager to develop memory devices that will take advantage of the extreme performance and low pin count of the Xccela Bus,” said Syed S. Hussain, director Flash Memory Marketing for Winbond Electronics Corporation America. “An open Xccela Bus interface standard reduces time and money for research and development so that a broad range of host and slave devices compliant with the specification can be delivered more quickly to customers. ”

“We are seeing a need for increasing the bandwidth performance of Non-Volatile Memory (NVM) devices for a new generation of applications. The Xccela Bus interface rises up to the challenge by delivering more than 4-5x the bandwidth of a Quad SPI device while maintaining a small footprint.” Said Mike Chen, Senior Director of Technical Marketing of GigaDevice Semiconductor. “We are delighted to be part of the Xccela Consortium to help drive a standard Octal SPI interface for the semiconductor industry.”

“Octal PSRAM enabled by the Xccela Bus interface provides a low-pin-count alternative to standard PSRAM and Low-Power SDR/DDR DRAM. It offers 3-5x fewer signal pins at comparable performance with lower overall cost, and represents a paradigm shift in the low-density RAM market.” said Charles Chang, Director of Sales and Marketing, AP Memory. “A single Xccela Bus supporting NOR flash memory, PSRAM, and NOR/PSRAM MCPs presents a more elegant design option and a strong value proposition, especially in the diverse IoT universe. AP Memory is committed to the Xccela Bus interface.”

The Xccela Consortium is open to all adopters, including semiconductor and electronics companies. Members have access to the initial specifications and can participate in the future specification definition and development. Visit the Xccela Consortium website for more details or contact Micron for additional information.