Cachelet™

AP memory provides cache memory DRAM, integrated into SoC to provide more cache requirement, but save SoC die area compared to SRAM.

 

Cachelet™ could be integrated with SoC by

  • 2.5D packaging
    • Panel level fan out
    • Silicon Interposer
  • 3D packaging
    • Chip on Wafer

For more information, please contact: enquiry@apmemory.com