AP Memory provides customized high-bandwidth low-power DRAM for SoC design targeting high bandwidth applications such as AI, HPC, data centers and networking. While having a memory capacity of more than 4GB, which is about 5-10 times the maximum on-die SRAM capacity on 7nm logic technology, VHM™ provides the widest bandwidth memory solution in the market.




The interface between SoC and VHM™ is VHMLInK™. VHMLInK™ which uses AP Memory defined protocol to access VHM™ is embedded in logic SoC design. VHMLInK™ is a digital IP core which allows SoC design to remain in its optimal process node without limitation.

3D Heterogeneous Integration

The integration of DRAM with SoC will use 3D heterogeneous stacking such as WoW (Wafer on wafer) or CoW (Chip on Wafer) technology. This technology realizes 3D silicon integration through wafer or chip stacking process. The tight bonding pitch enables better performance, lower power and latency.


WoW Technology


CoW Technology